About

I'm Yifan (亦凡) Yuan (袁), and I work at Meta's AI Systems Co-design team on future compute/AI infra systems architecture. My research focuses on hardware-software co-design for modern cloud datacenters, ranging from accelerators to I/O, memory, networking, and distributed systems.

Before Meta, I spent two years at Intel Labs (Systems Architecture Lab) as a research scientist. I received my PhD from ECE@UIUC (advised by Prof. Nam Sung Kim), and my undergraduate degree from Zhejiang University (ZJU), where I focused on computer architecture and VLSI design.

I grew up in Tianjin, a city in China with spirit of humor and optimism. I enjoy badminton, hiking, and cooking.

Publications

Full list (incl. US patents)
2025
  • Re-architecting End-host Networking with CXL: Coherence, Memory, and Offloading
    MICRO 2025 paper slides
    Peripheral Device In-network Computing Memory Technology Accelerator
  • DCPerf: An Open-Source, Battle-Tested Performance Benchmark Suite for Datacenter Workloads
    ISCA 2025 (Industry Session) paper slides
    Cloud Computing Performance Modeling
  • Dynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements and Guidelines
    ISCA 2025 paper slides
    Accelerator Cloud Computing In-network Computing
  • A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
    ISCA 2025 paper
    Memory Technology Peripheral Device Performance Characterization
  • M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems
    ASPLOS 2025 paper slides
    Memory Technology OS
2024
  • Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective
    MICRO 2024 paper
    Memory Technology OS Peripheral Device Accelerator Performance Characterization
  • Nomad: Non-Exclusive Memory Tiering via Transactional Page Migration
    OSDI 2024 paper, slides, and video
    Memory Technology OS
  • Intel Accelerator Ecosystem: An SoC-Oriented Perspective
    ISCA 2024 (Industry Session) paper slides
    Accelerator
  • A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
    ASPLOS 2024 paper slides
    Accelerator
  • BonsaiKV: Towards Fast, Scalable, and Persistent Key-Value Stores with Tiered, Heterogeneous Memory System
    VLDB 2024 paper
    Memory Technology
2023
  • Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Devices
    MICRO 2023 paper slides
    Memory Technology Peripheral Device Performance Characterization
  • STYX: Exploiting SmartNIC Capability to Reduce Datacenter Memory Tax
    ATC 2023 paper
    Accelerator Datacenter Tax
  • RAMBDA: RDMA-driven Acceleration Framework for Memory-intensive µs-scale Datacenter Applications
    HPCA 2023 paper slides
    Accelerator Cloud Computing
2022
  • IDIO: Network-Driven, Inbound Network Data Orchestration on Server Processors
    MICRO 2022 paper slides
    I/O Subsystem Peripheral Device
  • Unlocking the Power of Inline Floating-Point Operations on Programmable Switches
    NSDI 2022 paper and video slides
    ML Training In-network Computing
2021
  • Don't Forget the I/O When Allocating Your LLC
    ISCA 2021 paper slides
    I/O Subsystem Peripheral Device
  • QEI: Query Acceleration Can be Generic and Efficient in the Cloud
    HPCA 2021 paper slides
    Accelerator Cloud Computing
2020
  • Data Direct I/O Characterization for Future I/O System Exploration
    ISPASS 2020 paper slides video
    I/O Subsystem Peripheral Device Performance Modeling
2019
  • HALO: Accelerating Flow Classification for Scalable Packet Processing in NFV
    ISCA 2019 paper slides
    Accelerator Cloud Computing
  • Accelerating Distributed Reinforcement Learning with In-Switch Computing
    ISCA 2019 paper slides
    ML Training In-network Computing
2018
  • A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks
    MICRO 2018 paper slides
    ML Training In-network Computing

Professional Services and Activities

  • Program Committee: ASPLOS'27, ISCA'26, HPCA'2026, NSDI'2025, HPCA'2025, MICRO'2024 (ERC), ISCA'2024 (ERC and industry track), HPCA'2024, HPCA'2023 (ERC), EuroSys'2022 (shadow PC)
  • Reviewer: IEEE Transactions on Parallel and Distributed Systems (TPDS, 2022), IEEE Computer Architecture Letter (CAL, 2022–2023), ACM Transactions on Architecture and Code Optimization (TACO, 2024)